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ANDPS

Performs a bitwise AND operation on two packed single-precision floating-point values. The result is stored in the destination operand.

The following table covers what the source and destinations can be:

DO NOT support LOCK

This instruction requires the SSE extension to be supported by the processor. It is available in both 64-bit mode and compatibility mode.

To avoid undefined behavior or exceptions, ensure that the memory operands are aligned to 16 bytes; otherwise, a general-protection exception (#GP) may occur depending on the alignment check flag and the specific processor implementation. This instruction does not affect the EFLAGS register.