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ANDPD

Performs a bitwise logical AND operation on the lower 64 bits of two XMM registers. The result is stored in the destination register.

The following table covers what the source and destinations can be:

DO NOT support LOCK

This instruction is available in 64-bit mode and compatibility mode. It requires the SSE extension.

The operation only affects the lower 64 bits (quad word) of the XMM registers. The upper 64 bits of the destination register remain unchanged. Failure to account for the preserved upper bits may lead to logic errors when performing subsequent 128-bit operations.