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ANDNPS

Performs a bitwise AND operation between two packed single-precision floating-point values, but with the second operand (the source) bitwise inverted (NOTed). The result is then stored in the destination.

The following table covers what the source and destinations can be:

DO NOT support LOCK

This instruction is available in 64-bit mode and 32-bit mode. It requires the SSE3 instruction set extension; if the processor does not support SSE3, the execution of this instruction SHALL result in an invalid opcode exception.

The memory operand MUST be 16-byte aligned. If the memory address is not aligned to a 16-byte boundary, a general-protection exception SHALL occur. This instruction does not affect the floating-point status register or the EFLAGS register.