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ANDNPD

Performs a bitwise logical AND operation between the bitwise NOT of the first source operand and the second source operand, storing the result in the destination operand.

The following table covers the supported source and destination operands.

DO NOT support LOCK

This instruction is only available when the processor is operating in 64-bit mode or compatibility mode. It requires SSE4.1 support.

The operation is performed on the low 128 bits of the XMM registers. If a memory operand is used, the memory address SHALL be aligned to 16 bytes to avoid potential performance penalties or faults depending on the alignment check (AC) flag in the EFLAGS register.