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ANDN

Performs a bitwise AND operation between the NOT of the first source operand and the second source operand, storing the result in the destination operand.

The following table covers the supported source and destination operands:

DO NOT support LOCK

This instruction is only available when the processor is operating in 64-bit mode. It is NOT supported in compatibility mode or 32-bit mode.

The destination register MUST be the same as the second source operand to maintain the standard ANDN functional pattern, although the ISA allows the destination to be a different register. This instruction does not affect the EFLAGS register; specifically, the CF, OF, PF, and SF flags are NOT updated.