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AESIMC

Performs an Advanced Encryption Standard (AES) inverse mix-columns operation on the destination operand using the source operand.

The following table covers the supported source and destinations.

DO NOT support LOCK

This instruction is available only in 64-bit mode or 32-bit mode. It requires the AES-NI feature set to be enabled in the processor.

The instruction operates on 128-bit XMM registers. Ensure that the target processor supports the AES instruction set extension to avoid an #UD (Undefined Opcode) exception. Since the operation is performed on XMM registers, it does not affect EFLAGS.