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AESENC256KL

Performs one round of AES encryption using the 256-bit key variant. The instruction operates on the destination operand by performing a ShiftRows operation, a SubBytes operation, and an AddRoundKey operation using the source operand.

The table below covers what the source and destinations can be.

DO NOT support LOCK

The instruction is only available when the processor is operating in 64-bit mode or compatibility mode. It requires the AVX and AES-NI instruction set extensions to be enabled in the CPUID.

To avoid undefined behavior or General Protection faults, the destination and source registers MUST be of the same vector length. Using mismatched register sizes (e.g., mixing XMM and YMM) is NOT supported.