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AESENC128KL

Performs one round of AES encryption on a 128-bit state using a 128-bit round key. The operation consists of ShiftRows, SubBytes, MixColumns, and AddRoundKey.

The table after the description covers what the source and destinations can be.

DO NOT support LOCK

This instruction is available only when the processor supports the AES-NI and AVX extensions. It requires the processor to be in 64-bit mode or compatibility mode.

To avoid undefined behavior or crashes, ensure that the destination register is not used as a source for the round key in the same instruction unless the architectural implementation supports such dependency. The instruction operates exclusively on 128-bit XMM registers; attempting to use larger YMM or ZMM registers in a context where only 128-bit operations are supported may lead to performance degradation or unexpected state transitions.