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AESDECWIDE128KL

Performs a single round of the AES-128 decryption process on 128 bits of data using a specified round key, operating on the lower 128 bits of a 256-bit ZMM register.

The following table describes the supported source and destination operands.

DO NOT support LOCK

This instruction requires the AVX-512 side-channel-resistant or AES-NI extension support. It is available in 64-bit mode.

To avoid undefined behavior or faults, the destination register SHALL be a ZMM register if the instruction is used within an AVX-512 context to prevent potential alignment issues or state corruption associated with mixed SIMD widths. Ensure that memory operands are 16-byte aligned to avoid performance penalties or general protection faults.