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AESDEC256KL

Performs one round of the AES-256 decryption last round on the 128-bit data in the first operand using the 128-bit round key in the second operand.

The following table covers what the source and destinations can be.

DO NOT support LOCK

This instruction is only available if the processor supports the AES-NI instruction set. It operates on XMM registers and is supported in 64-bit mode and compatibility mode.

The instruction requires the destination register to be the same as the source register for in-place operations. Using an incorrect round key for the final round will result in incorrect decryption, as this instruction omits the MixColumns transformation required in intermediate rounds.