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ADDSS

Adds the scalar single-precision floating-point value from a source operand to the scalar single-precision floating-point value in a destination operand. The result is stored in the destination operand.

The following table covers what the source and destinations can be:

DO NOT support LOCK

This instruction is available in 64-bit mode and compatibility mode. It requires SSE support.

The instruction operates only on the lowest 32 bits of the XMM registers (f32); the remaining upper bits of the destination XMM register remain unchanged.

Precision and rounding are controlled by the MXCSR register. If the result cannot be represented in the destination format, it MAY trigger #O or #U. Inexact results SHALL trigger #P. Denormalized operands SHALL trigger #D.