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ADD

Adds the source operand to the destination operand and stores the result in the destination.

The following table specifies the supported source and destination operands:

Support LOCK

The instruction is available in 64-bit mode, 32-bit mode, and 16-bit mode (compatibility mode). When operating on memory, the instruction MUST NOT have both operands be memory locations; one operand MUST be a register or immediate.

The ADD instruction modifies the EFLAGS register. Specifically, it updates the Carry Flag (CF), Zero Flag (ZF), Sign Flag (SF), Overflow Flag (OF), and Parity Flag (PF) based on the result of the operation.

When using the LOCK prefix with a memory destination, the processor ensures an atomic read-modify-write cycle. Failure to use LOCK in multi-threaded environments when modifying shared memory can lead to race conditions. When using immediate values with memory destinations, the operand size MUST match the size of the memory region (mN).